SpiceXpanse: A Scalable, Automated Framework for Efficient Parameter Optimization and Modeling of RRAM Circuits
Published in IEEE Nanotechnology Materials and Devices Conference (NMDC) 2025, 2025
The extraction and modeling of device parameters for resistive random-access memory (RRAM) circuits are impeded by pronounced device variability and high-dimensional parameter spaces. Conventional SPICE workflows rely on manual file manipulation, limiting scalability and reproducibility. Here, we present SpiceXpanse, an open-source framework that automates RRAM model calibration by orchestrating configurable parameter exploration, parallel HSPICE execution, and interactive visualization. The modular optimization engine supports arbitrary sampling schemes, search heuristics, and composite loss definitions, enabling physically consistent fits while maintaining full process transparency. In a benchmark involving ten experimentally fabricated passive RRAM cells, SpiceXpanse reduced calibration time from multiple weeks to several hours on commodity hardware. As a case study, we applied a shadow-memory module to estimate per-device series resistances, aligning RESET thresholds at −2 V and significantly reducing dispersion. SpiceXpanse thus provides reproducible and scalable methodologies, significantly enhancing modeling accuracy and productivity for device characterization and circuit optimization, particularly beneficial for neuromorphic and in-memory computing research.
Recommended citation: S. S. Bezugam*, S. Choi, S. Menzel, and D. B. Strukov. IEEE Nanotechnology Materials and Devices Conference (NMDC) (2025) — Accepted. https://github.com/saibez/SpiceXpanse
